Taiwan Semiconductor Manufacturing
Combined average of Moat (AI Resilience), Growth, and Valuation scores.
Moat Score
Unmatched process-technology leadership at 3nm and below, with customer redesign costs making TSMC effectively irreplaceable for any leading-edge chip. The AI boom has deepened the design ecosystem moat as every major AI chip — from NVIDIA Blackwell to Google TPU to custom hyperscaler ASICs — runs exclusively on TSMC silicon. NVIDIA's reaffirmed TSMC exclusivity for its next-gen 'Rubin' architecture (citing the CoWoS advantage) and Intel 18A's persistent yield gap (50–55% vs. TSMC N2's 70%+) reinforce the thesis that no credible foundry alternative exists at the leading edge. Q2 2026 (GM 67.7%, FY26 guide raised to slightly above 40% USD) is the demand print of that monopoly, not a change in it.
TSMC's moat rests on three reinforcing pillars: Process Secrecy, Customer Lock-In, and Scale Economics:
- Process Technology Secrecy: TSMC's 3nm (N3E) and 2nm (N2, now in a steep H2 2026 ramp) process nodes represent decades of proprietary yield-learning that no competitor has replicated. Intel Foundry and Samsung are 1–2 generations behind on leading-edge logic, and that gap is widening, not closing. A14 (second-generation nanosheet) is targeting 2028 volume with A13/A12 extensions in 2029; A16 (backside power) remains on the 2026–27 path.
- Customer Redesign Lock-In: Apple, NVIDIA, AMD, and Qualcomm design their chips specifically for TSMC's PDK (process design kit). Re-taping a chip for a different foundry costs $500M–$1B+ and 2–3 years of engineering time — making switching economically irrational for any customer at leading-edge nodes. AI ASIC customers (Google, Amazon, Microsoft, Meta) are now in the same locked-in position.
- Yield-Learning Compounding: At leading-edge nodes, yield (the % of functional chips per wafer) is the decisive competitive variable. TSMC's decades of high-volume production have built an enormous yield-learning advantage that compounds with each new node — a gap competitors cannot close by simply spending more capital. Q2 2026 gross margin hit 67.7% (from 66.2% in Q1), reflecting this pricing power even as overseas fabs dilute.
Moat Verdict
TSMC is a direct and primary beneficiary of the AI era — every frontier AI model requires more TSMC-made chips, and the AI boom has structurally deepened the design ecosystem network effects. The AI-resilient moats (proprietary process data, regulatory lock-in from CHIPS Act and allied government partnerships, customer PDK embedding) are all intact or strengthening. Q2 2026 and the raised >40% FY26 guide are demand confirmation, not a new moat. The primary risk is geopolitical, not competitive: Taiwan cross-strait tensions and US tariff policy are the only plausible paths to moat disruption, and the $465B US investment commitment is actively reducing that structural risk.
94.7 resilient · 76.7 vulnerable · 80/20 = 91.1 · + 3 strength · = 94
Open a moat to read its note.
TSMC is a B2B manufacturer with no consumer-facing interface dependency.
TSMC's moat is in physical process technology, not embedded software logic.
TSMC does not derive competitive advantage from public data access.
TSMC employs over 70,000 engineers; leading-edge process engineers (N2/A16 yield engineers, EUV specialists) are among the scarcest technical talent on earth — AI cannot replace the physical intuition developed over decades at the fab floor. Demand for this talent intensifies with N2 and A14 ramps.
TSMC bundles leading-edge logic nodes with advanced packaging (CoWoS-S/L/X, SoIC, InFO) and design services (DRC), creating a one-stop advanced semiconductor manufacturing platform no competitor can match end-to-end. CoWoS has become effectively mandatory for AI accelerator chiplet integration.
Decades of process recipes and yield-learning data are trade secrets, and the volume behind them is unmatched: TSMC takes roughly 70% of global foundry revenue (TrendForce) and a larger share at the leading edge, so it runs more yield-learning wafers than every other foundry combined. N2 yield data from Hsinchu and Kaohsiung adds a new compounding layer.
CHIPS Act ($6.6B direct funding for Arizona), Japanese METI subsidies and the EU Chips Act all fund TSMC fabs, and the April 2026 US-Taiwan tariff framework scaled its committed US investment to ~$465B across 11 fabs for a 15% tariff, making TSMC a declared US national-security priority. Subsidies are not a barrier to rivals, though: the same CHIPS Act awarded Intel about $7.9B (converted into a US government equity stake in August 2025) and Samsung about $4.7B. The leading-edge lead is rated under scaleEconomics and proprietaryData; policy support every major foundry receives is intact. Re-rated from strong to intact.
The AI boom has structurally deepened the design ecosystem around TSMC processes. Every major AI hyperscaler (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) designs exclusively on TSMC N3/N2. The CoWoS ecosystem (TSMC packaging + SK Hynix/Micron HBM + NVIDIA/AMD logic) creates a 3-way supplier dependency. The entire AI chip startup ecosystem uses TSMC PDKs exclusively — structural moat deepening driven by AI concentration, not just market share.
Customers' entire chip design and validation workflows are embedded in TSMC's PDK. Re-taping a leading-edge chip for a competing foundry requires 2–3 years and $500M+ — making every tape-out a multi-year lock-in. AI ASIC customers have even longer design cycles (3+ years), deepening the embedding further.
TSMC is the de facto foundry of record for every leading-edge chip. Apple, NVIDIA, AMD, Qualcomm, MediaTek, and all major AI ASIC designers depend on TSMC for their most advanced products — no alternative system exists at scale. Intel 18A and Samsung SF2 remain 1–2 generations behind TSMC on yield at leading-edge nodes.
Leading-edge capex no rival can fund at the same pace — about $40B a year (2025 guidance $38–42B) — plus roughly 70% of global foundry revenue drives yield learning and unit cost down faster than Samsung or Intel Foundry. Scale is the heart of the process lead.
Buyers are enterprises choosing on switching cost, integration and performance, which the other pillars rate. The name carries reputation, not a price premium it could hold on brand alone.
Combined average of Moat (AI Resilience), Growth, and Valuation scores.
Moat Score
Unmatched process-technology leadership at 3nm and below, with customer redesign costs making TSMC effectively irreplaceable for any leading-edge chip. The AI boom has deepened the design ecosystem moat as every major AI chip — from NVIDIA Blackwell to Google TPU to custom hyperscaler ASICs — runs exclusively on TSMC silicon. NVIDIA's reaffirmed TSMC exclusivity for its next-gen 'Rubin' architecture (citing the CoWoS advantage) and Intel 18A's persistent yield gap (50–55% vs. TSMC N2's 70%+) reinforce the thesis that no credible foundry alternative exists at the leading edge. Q2 2026 (GM 67.7%, FY26 guide raised to slightly above 40% USD) is the demand print of that monopoly, not a change in it.
Growth Score
Q2 2026 delivered USD revenue of $40.20B (+33.7% YoY, +12% QoQ) at the high end of guide, net income +77.4% YoY, and gross margin 67.7%. Q3 guide is $44.6–45.8B with GM 65–67% as the N2 ramp dilutes ~3–4pp. Management raised FY2026 USD revenue growth to slightly above 40% from 30%+. The 3–5 year blend still decays from that spike toward the prior 25% USD CAGR through 2029, which is why the estimate stays 25–30% rather than the 40% currently on the tape.
Valuation Score
Re-marked at the $450.61 close on September 25, 2026 (the last IM25 mark before the rebalance): 65 on the unchanged $240 / $450 / $620 ladder, from 70 at the $412 reference the text below was written at. Only the price moved; the ladder and the thesis are not re-underwritten here. At $412 (August 19, 2026) TSMC sits ~8% below the revised $450 base and 82% of the way from the $240 bear toward base, a 70 on the piecewise scale. The July 16 print (Q2 $40.2B, FY26 guide >40%) is why the ladder moved up from $400/$560; the subsequent drift from the post-print ~$419 toward $412 restored a modest discount to the new base. ~26–28× a raised 2026E EPS path is still a premium to the semi median, now better supported by the print.
The Fabrication Monopoly
TSMC's moat rests on three reinforcing pillars: Process Secrecy, Customer Lock-In, and Scale Economics:
- Process Technology Secrecy: TSMC's 3nm (N3E) and 2nm (N2, now in a steep H2 2026 ramp) process nodes represent decades of proprietary yield-learning that no competitor has replicated. Intel Foundry and Samsung are 1–2 generations behind on leading-edge logic, and that gap is widening, not closing. A14 (second-generation nanosheet) is targeting 2028 volume with A13/A12 extensions in 2029; A16 (backside power) remains on the 2026–27 path.
- Customer Redesign Lock-In: Apple, NVIDIA, AMD, and Qualcomm design their chips specifically for TSMC's PDK (process design kit). Re-taping a chip for a different foundry costs $500M–$1B+ and 2–3 years of engineering time — making switching economically irrational for any customer at leading-edge nodes. AI ASIC customers (Google, Amazon, Microsoft, Meta) are now in the same locked-in position.
- Yield-Learning Compounding: At leading-edge nodes, yield (the % of functional chips per wafer) is the decisive competitive variable. TSMC's decades of high-volume production have built an enormous yield-learning advantage that compounds with each new node — a gap competitors cannot close by simply spending more capital. Q2 2026 gross margin hit 67.7% (from 66.2% in Q1), reflecting this pricing power even as overseas fabs dilute.
Moat Verdict
TSMC is a direct and primary beneficiary of the AI era — every frontier AI model requires more TSMC-made chips, and the AI boom has structurally deepened the design ecosystem network effects. The AI-resilient moats (proprietary process data, regulatory lock-in from CHIPS Act and allied government partnerships, customer PDK embedding) are all intact or strengthening. Q2 2026 and the raised >40% FY26 guide are demand confirmation, not a new moat. The primary risk is geopolitical, not competitive: Taiwan cross-strait tensions and US tariff policy are the only plausible paths to moat disruption, and the $465B US investment commitment is actively reducing that structural risk.
94.7 resilient · 76.7 vulnerable · 80/20 = 91.1 · + 3 strength · = 94
Open a moat to read its note.
TSMC is a B2B manufacturer with no consumer-facing interface dependency.
TSMC's moat is in physical process technology, not embedded software logic.
TSMC does not derive competitive advantage from public data access.
TSMC employs over 70,000 engineers; leading-edge process engineers (N2/A16 yield engineers, EUV specialists) are among the scarcest technical talent on earth — AI cannot replace the physical intuition developed over decades at the fab floor. Demand for this talent intensifies with N2 and A14 ramps.
TSMC bundles leading-edge logic nodes with advanced packaging (CoWoS-S/L/X, SoIC, InFO) and design services (DRC), creating a one-stop advanced semiconductor manufacturing platform no competitor can match end-to-end. CoWoS has become effectively mandatory for AI accelerator chiplet integration.
Decades of process recipes and yield-learning data are trade secrets, and the volume behind them is unmatched: TSMC takes roughly 70% of global foundry revenue (TrendForce) and a larger share at the leading edge, so it runs more yield-learning wafers than every other foundry combined. N2 yield data from Hsinchu and Kaohsiung adds a new compounding layer.
CHIPS Act ($6.6B direct funding for Arizona), Japanese METI subsidies and the EU Chips Act all fund TSMC fabs, and the April 2026 US-Taiwan tariff framework scaled its committed US investment to ~$465B across 11 fabs for a 15% tariff, making TSMC a declared US national-security priority. Subsidies are not a barrier to rivals, though: the same CHIPS Act awarded Intel about $7.9B (converted into a US government equity stake in August 2025) and Samsung about $4.7B. The leading-edge lead is rated under scaleEconomics and proprietaryData; policy support every major foundry receives is intact. Re-rated from strong to intact.
The AI boom has structurally deepened the design ecosystem around TSMC processes. Every major AI hyperscaler (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) designs exclusively on TSMC N3/N2. The CoWoS ecosystem (TSMC packaging + SK Hynix/Micron HBM + NVIDIA/AMD logic) creates a 3-way supplier dependency. The entire AI chip startup ecosystem uses TSMC PDKs exclusively — structural moat deepening driven by AI concentration, not just market share.
Customers' entire chip design and validation workflows are embedded in TSMC's PDK. Re-taping a leading-edge chip for a competing foundry requires 2–3 years and $500M+ — making every tape-out a multi-year lock-in. AI ASIC customers have even longer design cycles (3+ years), deepening the embedding further.
TSMC is the de facto foundry of record for every leading-edge chip. Apple, NVIDIA, AMD, Qualcomm, MediaTek, and all major AI ASIC designers depend on TSMC for their most advanced products — no alternative system exists at scale. Intel 18A and Samsung SF2 remain 1–2 generations behind TSMC on yield at leading-edge nodes.
Leading-edge capex no rival can fund at the same pace — about $40B a year (2025 guidance $38–42B) — plus roughly 70% of global foundry revenue drives yield learning and unit cost down faster than Samsung or Intel Foundry. Scale is the heart of the process lead.
Buyers are enterprises choosing on switching cost, integration and performance, which the other pillars rate. The name carries reputation, not a price premium it could hold on brand alone.
Growth Analysis
Growth Drivers
Key Risk
The April 2026 US-Taiwan tariff framework reduced import tariffs to 15% in exchange for scaling TSMC's US investment to ~$465B/11 fabs, and NVIDIA has reaffirmed TSMC exclusivity for Rubin citing CoWoS. Residual risk: if Intel 18A yields reach parity (>65%) by end of 2027 and a major AI ASIC customer (Google TPU, Amazon Trainium) shifts >15% of leading-edge wafer volume away from TSMC, the AI ASIC anchor thesis weakens — a 2027+ risk rather than a near-term one. Cross-strait tension is the other unmaterialised tail.
Score Derivation
88.3 base + 2.7 trajectory + 4 margin − 5 risk = 90
Base 88 (25–30% CAGR midpoint 27.5%) + 2.7 trajectory (AI accelerators and N2/N3 accelerating; overseas fabs stable) + 4 expanding margins (Q2 GM 67.7%) − 5 moderate residual geopolitical/yield-gap risk = 90. The FY26 40% print is charged in the measured series and then decayed in the estimate, not added as a TAM bonus.
AI Chip Tailwinds
FY2026 USD revenue growth raised to slightly above 40% on continued AI / leading-edge demand, including a CPU resurgence in AI data centers from agentic AI
Q3 2026 revenue guided $44.6–45.8B (+12% QoQ / ~37% YoY at midpoint); N2 steep ramp is the near-term volume driver and a 3–4pp GM headwind
A14 (2nd-gen nanosheet) on track for 2028 volume; A13/A12 extensions target 2029. CEO declined to raise the prior mid-to-high-50s AI-accelerator CAGR because demand is 'stronger and stronger' than the January figure
US-Taiwan tariff framework (April 2026) remains in force: committed US investment ~$465B across 11 fabs in exchange for a reduced 15% tariff; next-three-year capex 'even more significantly higher' than the last three
Price Scenarios (12–24 Months)
Valuation Analysis
Revised base of ~$450 reflects ~27–28× a higher 2026E EPS path after FY26 USD growth was raised to slightly above 40% (Q2 EPS $4.31/ADR). The geopolitical discount remains narrower than a year ago under the April 2026 tariff framework, though Taiwan cross-strait tensions are still a residual factor. ~$450.
Valuation Multiples
| Trailing P/E (GAAP) | ~30× |
| Forward P/E (NTM) | ~26× |
| PEG Ratio | ~1.0× |
| Price / Sales (NTM) | ~13× |
| Q2 CapEx | $15.7B |
At ~26× a raised forward, TSMC still trades at a premium to the semiconductor sector median (~20×), but the July 16 print validated the earnings ramp the July 3 analysis was waiting on. A PEG near 1.0× is fairly priced for a monopoly guiding 40% this year and ~25% through 2029. The gap between trailing and forward P/E continues to signal an earnings ramp as N2 scales.
Approximate figures as of August 19, 2026 (price ~$412).
Where We Are vs Targets
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US tariff escalation and Taiwan cross-strait tensions trigger customer diversification mandates; semiconductor cycle turns; multiple compresses to ~17× NTM earnings.
- Commerce Department enforces 50% domestic sourcing rule, forcing NVIDIA and AI ASIC designers to dual-source with Intel 18A or Samsung — TSMC loses 20%+ of AI wafer orders
- Global semiconductor downturn compresses advanced-node utilization below 80%; N2 ramp dilution worsens gross margin toward sub-55%
- China PLA exercises escalate toward blockade scenario, triggering a geopolitical risk premium expansion and P/E de-rating to ~17× NTM EPS
- Arizona fab cost overruns delay Phase 2; CHIPS Act funding faces clawback amid US political headwinds
N2/N2P ramp sustains the raised 2026 trajectory into 2027; AI chip demand keeps CoWoS at capacity; geographic diversification progresses without major disruption; ~27–28× 2026E EPS.
- AI accelerator demand (NVDA Blackwell Ultra, AMD MI400, hyperscaler ASICs) sustains N3/N2 utilization above 90% through 2026–27
- N2 steep ramp in H2 2026 converts the >40% FY26 guide; A14 stays on the 2028 volume path
- CoWoS capacity expansion absorbs demand backlog; advanced packaging grows as a larger revenue mix
- Arizona Fab 2 (3nm) progresses toward HVM in 2027, reducing geopolitical risk premium
Sovereign AI buildout drives unprecedented wafer demand; A14 becomes a larger, longer-lived node than N2; geopolitical discount partially unwinds as US fabs scale; ~30× 2027E EPS.
- Nations building sovereign AI capacity (Saudi Arabia, UAE, India, EU) create incremental 50,000+ wafer/month demand beyond the current customer base
- A14 and A12/A13 extensions win the next AI node race — Amazon, Google, Microsoft, Meta all anchor custom ASICs from 2028
- Geopolitical risk premium compresses as Arizona and Japan fabs reach 20%+ of leading-edge capacity, reducing Taiwan-concentration discount
- P/E re-rating toward ~30× as TSM is treated as critical AI infrastructure on a higher 2027E EPS path