Marvell Investor Day 2026: The $80 Billion Plan Leans on Interconnect

Marvell held its investor day on October 6 and raised its FY2028 revenue target to about $20 billion, up from $18 billion in August and above the $18.2 billion analysts expected. It also gave its first FY2031 framework, $70 to $90 billion, against an FY2026 base of $8.2 billion. The stock dipped 3% as the event began and traded about 6% higher later in the day. Most of the coverage told it as a custom chip story: Marvell building accelerators for hyperscalers, a Google agreement covering up to $120 billion of custom revenue through FY2033, and a raised FY2029 custom target of more than $12 billion.

I read the transcript differently. When you split the $80 billion midpoint by segment and set each piece against the market Marvell itself sized, the plan leans harder on interconnect than on custom chips. That matters for holders, because the two businesses fail in different ways.

Interconnect is the largest line in the plan, and it's the only one where the plan needs Marvell to reach more than half the market. In custom compute, the segment the headlines were about, it needs a bit more than one dollar in eight. Management framed it the same way. Chris Koopmans, Marvell's president, told the room "we are not an ASIC vendor" and said Marvell builds custom silicon for customers who also buy the rest of its platform. CEO Matt Murphy said that by FY2031 custom would be "much more balanced between XPU and XPU attach sockets."

An XPU is the accelerator itself, the chip doing the AI math. Attach chips sit beside it: network interface controllers, memory and storage controllers, I/O dies. Investing.com reported that management expects one to two attach sockets per XPU at prices near $1,000, and Bank of America's Vivek Arya wrote that he sees room above Marvell's $15 billion XPU-attach target for 2030. If those numbers hold, about half of the $30 billion custom line isn't the accelerator, and the accelerator itself is closer to a fifth of the whole plan.

The matrix doesn't separate the interconnect names from the accelerator names on embedding, and the reason sits in Marvell's own stock file. Its deepest pillar is grounded in custom chips co-designed with each hyperscaler across generations, with the Google agreement as the proof. Its DSP and SerDes franchise is rated a step lower, as a lead rather than a monopoly. So the framework, like most of the coverage, treats the accelerator relationship as the thing that locks customers in. I think the record of the last year points the other way, at least for Marvell.

At Amazon, the accelerator was the piece that got shared, and Marvell's memory and I/O pieces were the ones that survived. At Google, Marvell's new agreement reaches well past any accelerator into NICs, storage and memory controllers, chips that ship around the TPU whoever builds its core. Broadcom's accelerator book is the big exception, and I take it up below.

A hyperscaler that builds its own accelerator owns the part it cares about most, which is the architecture. Google designs the TPU core. The design partner turns that spec into a manufacturable chip and handles packaging with TSMC. That's skilled work, but a buyer can split it, and MediaTek was reported to win part of a TPU generation partly on costs 20–30% below other partners. For the buyer, switching costs a schedule risk on one generation, not a rewrite of its own systems.

• Optical DSPs are chosen by module makers and qualified into transceivers that have to interoperate with switches from several vendors. Futurum's read of the 1.6T race is that the DSP chosen now sets the optical design for the next two switching generations, so a win outlasts one accelerator cycle.
• Attach chips ride on the accelerator rather than compete with it. A NIC or memory controller that works across several accelerator generations ships whether Broadcom, MediaTek, Alchip or an in-house team wins the next one. That's how Marvell can sell into Google's TPU ecosystem without owning the TPU core.
• Marvell supports NVLink, UALink and Ethernet for scale-up, so it doesn't have to pick the winning accelerator to sell the link between them.

That's why a lost-accelerator headline and a lost-DSP headline shouldn't move Marvell by the same amount. The accelerator is roughly a fifth of the FY2031 plan. Interconnect is nearly half of it, at a share Marvell still needs to reach.

The first objection is Broadcom. If accelerator work were as easy to rebid as I'm arguing, Broadcom wouldn't have stayed Google's TPU partner since the program began, and it wouldn't be shipping accelerators to Google, Anthropic, OpenAI and Meta at once. Its AI revenue was $16.7 billion in the quarter to August 2, and Hock Tan said accelerators were 73% of it. Marvell's own Google agreement runs through FY2033 and starts with inference accelerators. If the accelerator turns out to be as sticky for Marvell as it has been for Broadcom, the custom line is the stronger half of the plan. My answer is partial. Broadcom brings its own SerDes, packaging and networking, so it may be the work around the accelerator that keeps it in the room. But one partner holding a buyer's accelerator for many generations is evidence against my mechanism, and I can't fully explain it away.

The second objection cuts closer. What Google gave MediaTek on the cost-focused TPU wasn't the core. It was I/O, SerDes and peripheral design, the edge-of-chip work I've been calling the sticky part. If a buyer will move that work to save 20–30%, attach and interface silicon may be no safer than the accelerator. My answer is that MediaTek took it on a new variant rather than replacing an incumbent mid-program, which is the Amazon pattern too. That distinction may not hold for long.

The third objection is that standards make DSPs substitutable. A PAM4 DSP has to meet IEEE and OIF specs so modules interoperate, and that's exactly what let Broadcom build a real second source. Broadcom's Taurus is a direct alternative to Marvell's 1.6T part, and Futurum thinks Broadcom could get a head start of six months or more on design wins over Marvell's next coherent DSPs. Needing 58% of a market with a capable second vendor is an aggressive assumption, not proof of lock-in. My answer is that qualification makes each module design sticky once won, but each new speed generation reopens the contest. The 1.6T cycle is that contest, happening now.

The fourth objection is the one I take most seriously: the DSP market could shrink under Marvell. Linear pluggable optics take the DSP out of the signal path. Co-packaged optics put the optical engines on the switch package itself. Broadcom has shipped co-packaged switches to a few hyperscalers including Meta since 2023, and Meta reported about 65% lower power per lane than retimed pluggables. Futurum notes Nvidia plans co-packaged optics in future Spectrum-X switches and is reported to be building some 1.6T DSPs in-house. If those designs win, the 58% would be a share of a smaller pie. Marvell bought Celestial AI to have an optical answer, but it said it has virtually no scale-up optics revenue today. I don't have a good answer here beyond timing: pluggables still carry the 1.6T generation, so this is a risk for the 3.2T cycle more than the current one.

Last, every market size in the first table is Marvell's own. A $65 billion interconnect market by 2030 assumes roughly 65% annual growth, and the $400 billion total assumes data center capex near $3 trillion. If capex flattens in 2027 or 2028, every line falls together and the split between interconnect and custom stops mattering. Morgan Stanley stayed at Equal-Weight after the event, which is a fair reminder that the size of the plan is the bigger bet than its mix.

I don't think the investor day changed what Marvell is. It's a connectivity company that uses custom work to get deeper into each hyperscaler, and its own segment split says so. That changes what to watch. An accelerator won or lost at Amazon, Microsoft or Meta will make a big headline and probably a big one-day move, as December did, but it touches roughly a fifth of the plan. What touches the rest is Marvell's position in 1.6T DSPs as module makers choose between it and Broadcom, how many attach chips ship per accelerator as the Google agreement starts to vest, and whether co-packaged optics take real volume in scale-out networks before 3.2T.

The same question sorts the rest of the cohort. Credo lives or dies on the same interconnect boundary. Broadcom's risk is the opposite one: a buyer like Google splitting more of each accelerator generation. Google is the customer that decides how much of each socket it rebids, and Nvidia is both a buyer of interconnect and a builder of its own.

I'll revisit this after Marvell's next quarterly report, looking for any update on the 1.6T ramp and the first sign of Google agreement revenue.